In the semiconductor industry, it is normally desirable to fabricate NMOS (N-type metal oxide semiconductors) and PMOS (P-type metal oxide semiconductor) devices with matching threshold voltages. In conventional semiconductor processing, the NMOS and PMOS threshold voltages are conventionally adjusted by a combination of channel implants and selective doping of a polysilicon gate. It is generally effective in adjusting the threshold voltages for PMOS devices but less effective for NMOS devices. To overcome these problems, dual metal gate CMOS (complementary MOS) transistors have been provided, with the metals forming the gates being selected based on their work functions.
Traditional metal gate transistors are normally fabricated by dry etching of metal or metal capped with polysilicon, to form the gate. Dry etching of metal is extremely challenging, as it is difficult to ensure that the metal dry etch stops properly on the ultra-thin gate dielectric, such as a gate oxide. This failure to stop the dry etch on the gate oxide results in the loss of silicon in source/drain areas, thereby causing increased leakage current.
These problems encountered in forming metal gate transistors are exacerbated when attempting to implement dual metal gate CMOS arrangements. As stated above, such metal dual metal gate CMOS arrangements are desirable to adjust the work function and the threshold voltages. However, the traditional approach for forming metal gate transistors is not readily applicable to forming dual metal gate CMOS transistors.
It has proven desirable to provide fully silicided gates in order to suppress the drive current lost to polysilicon depletion effects. However, in providing fully silicided gate electrodes to suppress the drive current, the work function for one of the conductivity type devices will be undesirably changed. For example, providing full silicidation of the polysilicon gate electrodes of NMOS devices and PMOS devices will operate to suppress the drive current lost to polysilicon depletion effects. However, although the gate electrode for the NMOS devices will have a desirable work function, the gate electrodes for the PMOS devices will have an undesirable work function. This concern limits the usefulness of fully siliciding the gate electrodes of both NMOS and PMOS devices in a semiconductor arrangement.
Furthermore, there are other concerns with fully silicided gates. These include the non-uniformity of the silicidation, and the potential for making the gate oxide dielectric layer unreliable. For example, over-silicidation will stress the gate oxide dielectric material, to the detriment of the reliability of the overall device.